For some years, there has been a demand in the semiconductor industry for system-on-chip devices. These devices incorporate multiple functions on a single chip. To achieve these functions, multiple transistor element types, each operated by a different power supply voltage, are mounted together. For example, some constructions include a peripheral region having I/O (Input/Output) device transistors that operate at a relatively high voltage, a step-down circuit to reduce the voltage, and a core region having logic device transistors that operate at a lower voltage.
Manufacturing reliable high-quality devices with high and low voltage transistors has proved challenging. High and low voltage transistors are formed with gate dielectrics having differing thicknesses and/or compositions. Processes that form gate dielectrics can have deleterious effects on previously formed gate dielectrics and their substrate interfaces. For example, growing a second gate dielectric can cause re-growth of a first gate oxide.
As semiconductor fabrication methods improve, it is becoming possible to fabricate transistors and other integrated circuit components with increasingly small dimensions. It is generally desirable to shrink component sizes as much as possible to reduce costs and improve performance. However, as transistor gates become smaller, they become less effective at turning transistors off. This can additionally lead to undesirable body leakage effects that increase the power consumption of an integrated circuit. Hardware-based approaches can help reduce body leakage and drain to source leakage. However, hardware-based approaches can result in an increase in circuit overhead and complexity. It would therefore be desirable to provide improved ways in which to reduce power consumption due to body leakage effects and source to drain leakage in programmable logic devices.